August 30, 2009


One of the joys of having my sort of background is receiving a steady stream of junk mail from the professional societies with sentences like these in the body:
"Design and synthesis of ICs considering factors such as: signal integrity, transmission line effects, POC, phase shifting, and sub-wavelength lithography [...] spare-cell strategies for ECO, decoupling capacitance and antenna rule fixing [...] Reliable clock tree generation and clock distribution methodologies for Gigaherz designs [...] EDA tools, design techniques, and methodologies, dealing with issues such as: timing closure, R,L,C extraction, ground/Vdd bounce, signal noise / crosstalk / substrate noise [...]"
Yes, all this from a flyer aimed at getting me to attend some international symposium or other last week. The really sad thing is I understand (or at least recognise) nearly all of what's written in these things. Getting a life's a low priority, I guess.

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